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Internal Design Service Team Supporting

Libraries
  • Standard Cell
  • I/O Library
  • SRAM
    - Bit-cell (0.5um, 0.35um)
    - Macro/reference circuit (0.35um): In development

IP/Memories

  • Emb-OTP & Emb-Fuse
    Self-designed Emb-OTP (0.5um)
    - Macro: 4K/8K/16K/32K/64K*8/12/16
    - Bit-cell & reference circuit
    - Custom service
    Emb-MTP & Emb-Fuse (partner designed): YMC
  • Emb-EEPROM, Emb-Flash (partner designed): YMC
  • Others: Please contact with our sales.

EDA

 PDK Support:
  Logic Design Circuit Design Layout Design Place & Route Layout Verification
Cadence Verilog model, Synopsys Timing model HSPICE model*, symbol for Cadence Composer or Mentor View Draw Tech file, Pcell* LEF file*
(Std cell & I/O library)		 Dracula CMD files*
Synopsys Un-support Frame View* (Astro/Apollo) Un-support
Mentor Graphic Un-support Un-support Calibre CMD files*
SpringSoft Laker Un-support Tech file, Mcell* Not Available Not Available
* In our PDK
SPECTRE model is available by request.
Mask Tooling Service

Design Partner

Gateway Silicon Inc. Gateway Silicon Incorporation ( GSI )
- IP service
- Turnkey Service (RTL to GDSII/Wafer/Turnkey, Gate to GDSII/Wafer/Turnkey)

Yield Microelectronics Corporation Yield Microelectronics Corporation ( YMC)
Embedded NVM Solution

By customer's request for providing design service support of other sites.
Please contact us for further inquiries.
   
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